Use descriptive net names for anything that isn't an obvious point-to-point connection
(e.g. USB_D+, nRESET, not Net-(U1-Pad3)).
Organize a non-trivial design into hierarchical sheets by subsystem (power, MCU, interfaces),
not as one flat sheet — a sheet a reviewer can't read at a glance is too big.
Keep signal flow left-to-right and power flow top-to-bottom where the layout allows it;
fight the autorouter's default placement rather than accept a schematic that reads
backwards.
Label every connector and test point with its function, not just a reference designator.
Use the _Small KiCad symbol variant for two-terminal passives (Device:C_Small,
Device:R_Small, Device:L_Small, Device:Crystal_GND24_Small, Device:LED_Small)
instead of the standard variant (Device:C, Device:R, Device:L, Device:Crystal_GND24, Device:LED) — it
draws a smaller, less cluttered symbol on the schematic sheet with no effect
on footprint or electrical behavior, purely a drawing convention.
Place a decoupling capacitor directly at the supply pin(s) of every active IC on the
schematic, wired point-to-point to that pin — not merely "somewhere on the power net". The
schematic is where this intent is recorded; the layout guideline
(guidelines/pcb_layout_design.md) covers physical placement distance.
Show bulk/reservoir capacitance and its net explicitly on the power sheet, not implied.
Add custom schematic symbol properties for sourcing data the generated make production-files
BOM export reads by name: LCSC (JLCPCB part number, e.g. C1000), Manufacturer (e.g.
Texas Instruments), and MPN (manufacturer part number, e.g. STM32F405RGT6). All three are
optional per symbol — an empty value renders as an empty BOM cell, not an error.
Populate at least LCSC or Manufacturer+MPN for any part you intend to have a fabricator
source automatically; a part with none of the three still appears in the BOM, just without
sourcing data a fab's auto-matching can use.
The generated project's make erc (kicad-cli sch erc) must run clean before a schematic
change is considered done — it is this project type's equivalent of a passing unit test (see
the kicad-drc-and-erc-as-quality-gates ADR).
Never suppress an ERC warning without a documented reason (a comment on the affected net or
pin, or an ERC exclusion entry with rationale) — an unexplained suppression hides the next
real regression the same way an empty catch block would in software.