Maintain creepage and clearance distances appropriate to the working voltage between
conductors at different potentials (consult IPC-2221 or the relevant safety standard for the
voltage class involved) — do not rely on the fabricator's default DRC clearance alone for
anything above low-voltage logic levels.
Keep the return current path continuous under every high-frequency or high-current net: never
route a ground-plane split, slot, or via field directly underneath a signal that needs a
low-impedance return.
Provide adequate copper pour/thermal relief for power components; check the fabricator's
minimum copper-to-edge clearance before finalizing the board outline.
Account for the DC-bias effect when selecting ceramic (X7R/X5R and similar) capacitors:
effective capacitance drops significantly as the applied DC voltage approaches the part's
rated voltage. Derate against the actual operating voltage, not the printed capacitance
value — a "10 µF" part can easily deliver a fraction of that at its rated voltage.
Prefer a rated voltage comfortably above the actual rail voltage (a common rule of thumb is
2x) specifically to keep DC-bias derating in a region where the part still performs close to
its nominal value.
Route differential traces with matched length (length-matching within the tolerance the
interface's specification requires) and a constant spacing/width to hold characteristic
differential impedance constant along the pair.
Avoid routing a differential pair through a layer or via transition that breaks its reference
plane; keep both traces of a pair on the same layer for as much of their length as possible.
The generated project's make drc (kicad-cli pcb drc) must run clean (accounting for any
explicitly documented exclusion) before a layout change is considered done — the PCB-side
counterpart to make erc, and this project type's equivalent of a passing unit test (see the
kicad-drc-and-erc-as-quality-gates ADR).
A freshly scaffolded project's PCB has no board outline yet, so its first make drc run
reports exactly one expected violation ("malformed outline") until a board outline is drawn —
this is not a generator defect.